The present invention relates to an interleaving technique involved in digital modulation and demodulation, especially to a transmitter and a receiver capable of performing the unified interleave and deinterleave without employing an interleave method corresponding to a multiplexing scheme based on each transmission mode when implementing multiplex transmission combining a plurality of transmission modes with different error endurance.
FIG. 4 shows a multiplexed signal structure in which a frame structure is comprised of one frame including 48 slots and one super frame is structured by eight frames, for example. Here, a slot is a memory area for storing a packet consisting of 204 bytes adding a 16-byte RS(204, 188) error correction code to a 188-byte MPEG-2 TS packet. In digital transmission using a broadcasting satellite, it is assumed that the slots of the same number of each frame in a super frame, may use the same type transmission mode including the modulation scheme and error correction code, and four types of transmission modes can be used at maximum in one super frame. In addition, the transmission modes in the super frame are flexibly varied by reporting those modes from a transmitting side to a receiving side by using a control signal called a TMCC signal contained in the second previous super frame.
FIG. 5 shows the structure of a modulated signal generated from the multiplexed signal. In this case, the multiplexed data is subjected to interleaving in the transmitter side and deinterleaving in the receiving side in order to derive the full power of Reed-Solomon (RS) codes, typical external codes, by distributing burst errors which occur when the number of bit errors in the transmission channel are beyond the error correcting capability of a Viterbi decoder or a trellis decoder used for error correction in the receiver. For example, interleaving of depth eight is implemented by forming interleave frames at every eight slots using the same type transmission mode in a frame, and by reading out of the column the data of the interleave frames written into a row in a two dimensional memory. (When the number of the slots using the same type transmission mode is less than eight in a frame, or the number of the remaining slots is less than eight when the interleave frames are formed every eight slots in sequence, the interleave frame is structured in addition to slots of a frame which will be described later.
As structural examples, the implementing interleave process will now be described with reference to FIGS. 6 and 7. FIG. 6 shows an example in which 46 slots are transmitted by TC-8 PSK and one slot is transmitted by QPSK subjected to convolutional encoding with a coding rated of xc2xd, and further, one slot is regarded as a dummy slot. FIG. 7 shows an example in which 44 slots are transmitted by TC-8 PSK and one slot is transmitted by BPSK subjected to convolutional encoding with a coding rate of xc2xd, and further, three slots are regarded as dummy slots.
In either example, as for the one slot transmitted by QPSK or BPSK, one interleave frame is formed in one super frame. To match the timing of signals after the interleaving, a first-in-first-out (FIFO) memory for storing data with a length of the super frame {(data length of assigned slots)-(length of the interleave frame)} is necessary for the greater assigned slot number (in the above example, the 46 slots or 44 slots data transmitted by the TC-8 PSK).
Since the interleave frame is 204xc3x978 bytes, a FIFO memory is comprised of 204xc3x9746xc3x978xe2x88x92204xc3x978=73440 bytes in the example of FIG. 6, and shows a FIFO memory is comprised of 204xc3x9744xc3x978xe2x88x92204xc3x978=70176 bytes in the example of FIG. 7, thus performing the interleave process by once storing the data amount close to one super frame every each transmission mode.
However, the capacity of the FIFO memory changes according to the assigned slot number for each of transmission modes in the frame, and a controller controlling the interleave process should be needed because address control is changed according to the change of the capacity of the FIFO memory, thereby complicating a circuit structure.
Therefore, an object of the present invention is to provide a transmitter and a receiver implementing an interleave process simply without changing the circuit configuration by changing the assigned slot number according to the transmission mode in each frame.
In the first aspect of the present invention, there is provided a transmitter applicable to a transmission system capable of transmitting digital data (called the transmission coded signal), which are encoded by using different types of error correction codes and modulated by different types of modulation with schemes, as packet units in the multiplexed data with a frame structure consisting of N packets, said transmitter performing interleaving of a super frame unit, and comprising:
means for forming an interleave frame by combining packets corresponding to the same slot number in each frame;
write means for sequentially writing data according to a frame number of the interleave frame into a two-dimensionally arrangeable memory along a row or a column direction; and
readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along a column or row direction different from the row or column direction of said write means.
In the second aspect of the present invention, there is provided a receiver applicable to a transmission system capable of transmitting digital data (called transmission coded signal), which are encoded by using different types of error correction codes and are modulated by different types of modulation techniques, as packet unit in the multiplexed data with a frame structure consisting of N packets, said receiver performing deinterleaving of a super frame unit, and comprising:
means for forming a deinterleave frame by combining packets corresponding to the same slot number in each frame;
write means for sequentially writing data according to a frame number of the deinterleave frame into a two-dimensionally arrangeable memory along the column or row direction corresponding to the readout direction of an interleave process during transmission; and
readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along the row or column direction different from the column or row direction of said write means corresponding to the writing direction of the interleave process during transmission.